1. Field of the Invention
The present invention relates to a DLL (Delay-Locked Loop) circuit.
2. Background Art
A DLL circuit can control the delay of a signal. The DLL circuit is used, for example, for delaying the internal clock of a circuit device to synchronize the internal clock to an external clock of the circuit device. The performance of the DLL circuit can considerably affect the performance of a high-speed memory such as a DDR (Double Data Rate) memory.
Typically, the DLL circuit is provided with a delay line which includes plural delay units connected in series with each other. In the delay line, a reference signal propagates from a delay unit in an earlier stage to a delay unit in a later stage, and each delay unit outputs a delayed signal of the reference signal. The DLL circuit can decrease the delay of the reference signal, by employing a delayed signal output from a delay unit in an earlier stage. On the other hand, the DLL circuit can increase the delay of the reference signal, by employing a delayed signal output from a delay unit in a later stage. Hereinafter, a delay unit in an earlier stage is referred to as an earlier delay unit, and a delay unit in a later stage is referred to as a later delay unit.
Such a DLL circuit has a problem that considerable electric power is wasted on the delay line. In the DLL circuit, even when a delayed signal output from an earlier delay unit is used, the reference signal propagates to a later delay unit. In other words, the reference signal propagates to delay units located after a delay unit that outputs a delayed signal to be used, although they do not need the supply of the reference signal. Consequently, delay units that do not need to operate uselessly operate to waste power.
Therefore, an idea has been proposed that provides a blocking circuit in the delay line. The blocking circuit can switch between passing a reference signal (delayed signal) from a preceding stage to a subsequent stage and blocking the reference signal (delayed signal). In this case, the DLL circuit is provided with a delay line including plural delay units connected in series with each other and a blocking circuit inserted between those delay units.
In such a DLL circuit, wasted power consumption on the delay line is reduced. However, in this case, the delay time of each delay unit must be made equal to the delay time of the blocking circuit in order to enable the blocking circuit to serve as a delay unit. To make the delay time of each delay unit equal to that of the blocking circuit, the delay time of each delay unit must be increased, or the delay time of the blocking circuit must be decreased. The blocking circuit includes a circuit element for implementing the blocking function. Therefore, the delay time of the blocking circuit that has both blocking function and delaying function usually cannot be reduced to a value equal to the delay time of a delay unit that has only the delaying function. Accordingly, to make the delay time of each delay unit equal to that of the blocking circuit, in general, the delay time of each delay unit must be increased.
The equalized delay time is the minimum unit of delay time that the delay line can adjust. In other words, the delay time adjusted by the delay line has an error equal to the equalized delay time at maximum. This causes jitter in the DLL circuit that includes plural delay units and the blocking circuit. Therefore, the DLL circuit has a problem that jitter increases while wasted power consumption on the delay line is reduced. This is because the delay time of each delay unit needs to be increased in order to make the delay time of each delay unit equal to that of the blocking circuit in the DLL circuit, which increases the minimum unit of delay time that the delay line can adjust. A large jitter is a problem when handling an RF signal, in particular.
JP-A H11-272355 (KOKAI) discloses a clock synchronization delay control circuit and a clock synchronization delay control method that prevent wasteful consumption of electric power.